Register descriptions

PM0068

26/31

Doc ID 17100 Rev 2

3.10

Flash status register2 (FLASH_SR2)

This register is dedicated to Flash memory bank 2.

Address offset: 0x4C

Reset value: 0x0000 0000

Bits 31:0 FKEYR: FPEC key for bank 2

These bits represent the keys to unlock the FPEC.

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

Reserved

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Reserved

EOP

WRPRT

ERR

Res.

PG

ERR

Res.

BSY

rw

rw

rw

r

Bits 31:6 Reserved, must be kept cleared.

Bit 5 EOP: End of operation

Set by hardware when a Flash operation (programming / erase) is completed. Reset by

writing a 1

Note: EOP is asserted at the end of each successful program or erase operation

Bit 4 WRPRTERR: Write protection error

Set by hardware when programming a write-protected address of the Flash memory.

Reset by writing 1.

Bit 3 Reserved, must be kept cleared.

Bit 2 PGERR: Programming error

Set by hardware when an address to be programmed contains a value different from

'0xFFFF' before programming.

Reset by writing 1.

Note: The STRT bit in the FLASH_CR2 register should be reset before starting a

programming operation.

Bit 1 Reserved, must be kept cleared

Bit 0 BSY: Busy

This indicates that a Flash operation is in progress. This is set on the beginning of a Flash

operation and reset when the operation finishes or when an error occurs.