Configuring ADC registers for conversion

AN3023

14/23

Doc ID 16113 Rev 1

Buffered continuous mode

The buffered mode is enabled in the continuous conversion mode if bit DBUF = 1 in the

ADC_CR3 register. The data buffer registers are filled with the results for up to 16

consecutive conversions performed on a single channel.

Example 5

●

●

●

Buffered continuous mode for channel 3

●

Left alignment

●

Starting ADC by software

For Example 5, the ADC registers should be configured as follows:

ADC_CR1:SPSEL[2:0] = 010

ADC_CSR:CH[3:0] = 0011

ADC_CR1:ADON = 1

ADC_CR1:CONT = 1

ADC_CR3:DBUF = 1

ADC_CR2:ALIGN = 0

ADC_CR1:ADON = 1

Wait (ADC_CSR:EOC = 1)

The results of the 16 consecutive conversions should be read from on ADC_DBxRH and

ADC_DBxRL registers (x = 0..15) before the end of the next conversions. The OVR flag is

set if one of the buffer registers is overwritten.

Analog watchdog

In continuous mode, the analog watchdog is always enabled. The AWD analog watchdog

flag is set if the analog voltage converted by ADC is out of the guard band limited by low and

high threshold values. The low and high threshold values are programmed in the ADC_HTR

and ADC_LTR registers.

Figure 5.

Analog watchdog

The ADC_HTR and ADC_LTR values can be calculated by the formula

,

Analog voltage

HTR

LTR

High threshold

Guarded area

Low threshold

ADC_xTR

V

AIN

V

REF+

V

REF-

–

-----------------------------------------

2

N

1

–

()

⋅

=