AN2504 datasheet(10/14 Pages) STMICROELECTRONICS

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Simulation of the Reset Time-out Period

AN2504 - Application note

10/14

The voltage on the STM1061N output resp. capacitor, VCAP, rises as capacitor is charged.

When it reaches input high voltage trip point of the MCU (time t3), the high state is detected.

If there is no RC element on the output, the OUT pin goes high at the time t2. That is why

simulated reset time-out period is t3-t2.

Use following formula for determining the correct capacitor value:

where,

C = Capacitor of RC element in Farads,

R = resistor of RC element in Ohms,

t = desired time-out period (t3-t2) in seconds,

VCC = supply voltage,

VIH = input voltage trip point for the MCU

ln = natural logarithm.

Example:

The STM1061N27WX6F is used to monitor a 3V supply voltage. The MCU detects input

high state at VIH =0.7·VCC = 0.7·3V = 2.1V. Desired time-out period is 140ms. An R = 100Ω

resistor is chosen.

The value of the capacitor is following:

The closest higher capacitance value from the most common E12 series (i.e. C = 1.2µF) is

chosen. The time-out delay will be slightly greater by choosing a higher value of capacitor.

Remember that this circuitry should be used only for temporary purposes. In the case of real

need of time-out delay the usage of reset device is highly recommended as mentioned in

the Introduction.

–

--------------------------

⋅

--------------------------------------------

VCC VIH

–

--------------------------

⋅

-------------------------------------------

140

–

⋅

100

32.1

–

-----------------

⋅⋅

---------------------------------------------------------

1.16

–

⋅

1.16

µF

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