UPD6462GS datasheet(52/60 Pages) NEC

No. de pieza	UPD6462GS

Descripción Electrónicos	CMOS LSI CHIP FOR CAMCORDER ON-SCREEN CHARACTER DISPLAY 12 ROWS x 24 COLUMNS

PDF	60 Pages

Scroll/Zoom	100%

Fabricante Electrónico	NEC [NEC]

Página de inicio	http://www.nec.com/

Logo

52 / 60 page

µPD6461, 6462

POWER-ON CLEAR SPECIFICATIONS

VDD

tPCLL

0 V

VDD

0 V

VDD

0.8 VDD

0.16 VDD

PCL

EXTERNAL CLOCK INPUT

Timing for external clock input (valid when selected with mask option)

Note

10% of the external clock cycle

Example: When the external clock frequency is 8 MHz

Clock cycle = 125 ns

The maximum slew rate is 10% of 125 ns, giving 12.5 ns.

Remarks 1. Keep the external clock in phase with the rising edges of Hsync.

2. Design the input of Hsync so that noise of more than 100 ns is suppressed.

3. When using an external clock, leave the OSCOUT pin open.

Parameter

PCL pin low level hold time

Conditions

Min.

Typ.

Max.

Unit

µs

Symbol

tPCLL

Parameter

Time from external clock fall to synchro-

nizing signal rise

Time from synchronizing signal rise to

external clock fall

tS (rising slew rate)

Conditions

Min.

Typ.

Max.

Unit

Symbol

tC-H

tH-C

Note

tC-H

tH-C

50 %

Hsync

External

clock

10 %

90 %

UPD6462GS Datasheet(PDF) 52 Page - NEC

UPD6462GS Datasheet(HTML) 52 Page - NEC

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Descarga

Enlace URL