2

DICE/DWF SPECIFICATION

RH101A

DICE ELECTRICAL TEST LI ITS

©LINEAR TECHNOLOGY CORPORATION 2003

Wafer level testing is performed per the indicated specifications for dice. Considerable differences in performance can often be observed for dice versus

packaged units due to the influences of packaging and assembly on certain devices and/or parameters. Please consult factory for more information on

dice performance and lot qualifications via lot sampling test procedures.

Dice data sheet subject to change. Please consult factory for current revision in production.

I.D.No. 66-13-0101

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

LT/LT 0203 PRINTED IN USA

10Krad(SI)

20Krad(SI)

50Krad(SI)

100Krad(SI)

200Krad(SI)

SYMBOL

PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX UNITS

Post-Irradiation (Note 4)

Input Offset Voltage

22223

mV

Input Offset Current

10

10

10

10

20

nA

Input Bias Current

75

75

100

200

400

nA

CMRR

Common Mode

80

80

80

80

80

dB

Rejection Ratio

PSRR

Power Supply

8080808080

dB

Rejection Ratio

Large Signal Voltage Gain

5050505025

V/mV

Maximumm Output

±12

±12

±12

±12

±12

V

Voltage Swing

±10

±10

±10

±10

±10

V

Supply Current

33333

mA

Note 1: Unless otherwise noted, all measurements are made with unity

gain compensation (C1 = 30pF); these specifications apply for

20V.

Note 2: For supply voltages less than

±15V, the maximum input voltage is

equal to the supply voltage.

Note 3: Refer to LTC standard product data sheet for all other applicable

information.

Note 4: The post-irradiation table is for lot qualification based on sample

lot assembly and testing only. Contact LTC marketing for more detail.