Application code structure

AN4231

12/22

DocID024130 Rev 2

3.2.2

Clock Generation Module

This function allows enabling all modes configuring in the RUNPC[0] mode, all peripheral on

and to jump to the PLL configuration function.

Figure 6. CGM init function

3.2.3

PLL configuration

This function allows to select the clock source for the PLL. In this case the PLL is driven by

the FXOSC oscillator at 40 MHz.

Then it configures the RUN[0] mode in order to enable the external oscillator, turning on the

PLL and setting the PLL as system clock.

The CGM module allows to set the several dividers (Input, loop and output) in order to set

the output of the PLL to be at 120 MHz frequency.

Two keys are written in the Mode Entry MCTL register In order to complete the mode entry.

Last part of the function configures the PA0 pin to be a clock out pin where it is possible to

measure the PLL frequency divided by four.