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UPD16633B Datasheet(PDF) 13 Page - NEC |
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UPD16633B Datasheet(HTML) 13 Page - NEC |
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13 / 20 page ![]() 13 µµµµPD16633B Electrical Specifications (TA = –10 to +75°C, VDD1 = 3.3 V ±±±± 0.3 V, VDD2 = 10.5 V ±±±± 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Output Voltage Deviation Note 1 ∆VO Input data ±5 ±20 mV Average Output Voltage Variation Note 2 ∆VAV Input data ±10 mV Output Voltage Range VO Input data 0.1 VDD2 – 0.1 V Logic Part Dynamic Current Consumption IDD1 VDD1, No loads 1.6 10.0 mA Driver Part Dynamic Current Consumption 1 Notes 3, 4 IDD21 VDD2 = 10.5 V ± 0.5 V, No loads 4.4 8.0 mA Driver Part Dynamic Current Consumption 1 Notes 3, 4 IDD22 VDD2 = 13.5 V ± 0.5 V, No loads 6.4 10.0 mA Notes 1. The output voltage deviation refers to the voltage difference between adjoining output pins when the display data is the same (within the chip). 2. The average output voltage variation refers to the average output voltage difference between chips. The average output voltage refers to the average voltage between chips when the display data is the same. 3. The STB cycle is defined to be 20 µs at fCLK = 40 MHz. The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the measured values in the dot checkerboard input pattern. 4. Refers to the current consumption per driver when cascades are connected under the assumption of XGA single-sided mounting (10 units). Switching Characteristics (TA = –10 to +75°C, VDD1 = 3.3 V ±±±± 0.3 V, VDD2 = 10.5 V ±±±± 0.5 V, VSS1 = VSS2 = 0 V) Parameter Symbol Condition MIN. TYP. MAX. Unit Start Pulse Delay Time tPLH1 CL = 25 pF 10 15 ns Driver Output Delay Time 1 tPLH2 CL = 50 pF, RL = 50 k Ω 6.6 11 µs Driver Output Delay Time 2 tPLH3 CL = 50 pF, RL = 50 k Ω 10 17 µs Driver Output Delay Time 3 tPHL2 CL = 50 pF, RL = 50 k Ω 6.4 11 µs Driver Output Delay Time 4 tPHL3 CL = 50 pF, RL = 50 k Ω 9.1 17 µs Input Capacitance 1 CI1 STHR (STHL) excluded, TA = 25°C 6.4 15 pF Input Capacitance 2 CI2 STHR (STHL), TA = 25°C 6.3 15 pF |
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