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AD5060 Datasheet(PDF) 5 Page - Analog Devices

No. de pieza AD5060
Descripción Electrónicos  Fully Accurate 14-/16-Bit VOUT nanoDAC SPI Interface 2.7 V to 5.5 V, in an SOT-23
PDF  24 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD5060 Datasheet(HTML) 5 Page - Analog Devices

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AD5040/AD5060
Rev. A | Page 5 of 24
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit1
Unit
Test Conditions/Comments
t12
33
ns min
SCLK cycle time
t2
5
ns min
SCLK high time
t3
3
ns min
SCLK low time
t4
10
ns min
SYNC to SCLK falling edge setup time
t5
3
ns min
Data setup time
t6
2
ns min
Data hold time
t7
0
ns min
SCLK falling edge to SYNC rising edge
t8
12
ns min
Minimum SYNC high time
t9
9
ns min
SYNC rising edge to next SCLK fall ignore
1 All input signals are specified with tr = tf = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 30 MHz.
t4
t3
t2
t5
t7
t6
D0
D1
D2
D22
D23
SYNC
SCLK
t9
t1
t8
D23
D22
DIN
Figure 2. AD5060 Timing Diagram



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