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28F008B3 Datasheet(PDF) 42 Page - Intel Corporation |
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28F008B3 Datasheet(HTML) 42 Page - Intel Corporation |
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42 / 49 page ![]() SMART 3 ADVANCED BOOT BLOCK–BYTE-WIDE E 42 PRELIMINARY ADDRESSES [A] CE#(WE#) [E(W)] OE# [G] WE#(CE#) [W(E)] DATA [D/Q] RP# [P] IH V IL V IH V IL V IH V IL V IH V IL V IL V IL V IN D IN A IN A Valid SRD IN D IH V High Z IH V IL V V [V] PP PPH V PPLK V PPH V1 2 WP# IL V IH V IN D AB C D E F W8 W6 W9 W3 W4 W7 W1 W5 W2 W10 W11 (Note 1) (Note 1) 0605-016 NOTES: 1. CE# must be toggled low when reading Status Register Data. WE# must be inactive (high) when reading Status Register Data. A. VCC Power-Up and Standby. B. Write Program or Erase Setup Command. C. Write Valid Address and Data (for Program) or Erase Confirm Command. D. Automated Program or Erase Delay. E. Read Status Register Data (SRD): reflects completed program/erase operation. F. Write Read Array Command. Figure 15. AC Waveform: Program and Erase Operations |
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