ICS1523MLF datasheet(2/21 Pages) ICST

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Video Clock Synthesizer with I2C Programmable Delay

MDS 1523 Y

Revision 110905

Integrated Circuit Systems

525 Race Street, San Jose, CA 95126

tel (408) 297-1201

www.icst.com

ICS1523

Section 1 Operational Description

1.1 Naming Conventions

0xY = Register Index Y(hex)

0xY:Z = Register Index Y(hex), bit Z

0xY:Z~Q = Register Index Y(hex), bit Z to Q

1.2 Overview

The ICS1523 is a general purpose, high-performance,

I2C programmable clock generator. It also addresses

stringent graphics system line-locked and genlocked

applications and provides the clock signals required by

high-performance analog-to-digital converters.

Included are a phase-locked loop (PLL) with an over

500MHz voltage controlled oscillator (VCO), a Dynamic

Phase Adjust to provide (DPA) output clocks with a

programmable phase delay with respect to the input

HSYNC. This delay occurs on all PLL outputs including

the differential (PECL) and single-ended (SSTL_3)

high-speed clock outputs and the FUNC output.

The ICS1523 has the ability to operate in line-locked

mode with the HSYNC input or in frequency synthesis

mode with the OSC input with a 7 bit input divider. See

Section 6, “OSC Divider and REF”

1.3 Phase-Locked Loop (PLL)

The phase-locked loop has a very wide input frequency

range (8 kHz to 100 MHz). Not only is the ICS1523 an

excellent, general purpose clock synthesizer, but it is

also capable of line-locked operation.

Figure 1-1

PLL Functional Blocks

1.4 Voltage Controlled Oscillator (VCO)

The heart of the ICS1523 is a VCO. The VCOs speed

is controlled by the voltage on the loop filter circuit. This

voltage is controlled by the charge pump (CP) and will

be further described later in this section.

1.5 Charge Pump (CP) and COAST Input

The CPen bit and COAST input pin can enable and

disable the Charge Pump as needed. See Register

0:7-6. This is for maintaining the correct speed clock

outputs in the absence of reliable HSYNC inputs and is

useful for skipping vertical blanking intervals. These

intervals can have double frequency serration pulses or

even be missing HSYNC pulses completely. The

charge pump is asynchronously disabled and

synchronously re-enabled on the second input HSYNC

after the disable signal goes invalid.

1.6 VCO Divider (VCOD)

The VCOs clock output is first passed through the VCO

Divider (VCOD). The VCOD allows the VCO to operate

at higher speeds than the required output clock. The

VCOD has no effect on the speed of the output clocks,

but it increases the VCO frequency, thereby reducing

jitter and allowing VCO operation between 100 to 500

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