HM17CM256 datasheet(13/111 Pages) HYNIX

13 / 111 page

HM17CM256

- 13 -

PIN DESCRIPTION 4

No.

NAME

I/O

FUNCTION

Segment drive port

Segment output from display RAM data

mode

Non-lighted

lighted

Normal

Reverse

The output level is selected among VLCD, V2, V3, VSS by the

combination of FR signal and RAM data

(B/W mode)

FR signal

display RAM data

Normal mode

VLCD

VSS

Reverse mode

VLCD

VSS

174~557

SEGA0~SEGA127,

SEGB0~SEGB127,

SEGC0~SEGC127

164~169,

562~567

SEGSA0~SEGSA3,

SEGSB0~SEGSB3,

SEGSC0~SEGSC3

Dummy segment driver output

Located at both side of segment drivers, used for edge

display.

Common driver output

The output level is selected among VLCD, V1, V4 and VSS by

the combination of FR and scan data.

data

Output level

VSS

VLCD

162~137,

132~119,

568~594,

3~15

COM0~COM79

163

COMI0

Common drive output for icon display

COMI1

Common drive output for icon display

65,

OSC1,

OSC2

External reference clock input pin

Open when using internal oscillator clock or used as slave

device.

In this case, OSC1 goes to VSS level.

Connect external oscillating source to OSC1 port or connect

resistor between OSC1 and OSC2 when using external

oscillator.

Input / output pin for display timing clock

Output clock from master device is applied to slave chip

through CLK pin when used as master / slave mode.

M/S

mode

CLK

master

output

slave

input*

CLK

I/O

*input from master chip’s CLK output

(port No. 1,2,133,134,135,136,170,171,172,173,558,559,560,561,595,596 is dummy port.)

HM17CM256 Datasheet(PDF) 13 Page - Hynix Semiconductor

HM17CM256 Datasheet(HTML) 13 Page - Hynix Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL