Address 5: Bus And Status

READ

7

6

5

4

3

2

1

0

END

DMA

DMA

REQUEST

PARITY

ERROR

IRQ

PHASE

MATCH

BUS ERROR

ATN

ACK

WRITE

–START DMA SEND

7

6

5

4

3

2

1

0

XXXXXXXX

Address 6: Input Data

READ

7

6

5

4

3

2

1

0

LDB7

LDB6

LDB5

LDB4

LDB3

LDB2

LDB1

LDB0

LATCH SCSI DATA. The register represent the complement of the active low SCSI data bus.

WRITE

–START DMA TARGET RECEIVE

7

6

5

4

3

2

1

0

XXXXXXXX

Address 7:

READ

–RESET PARITY/INTERRUPT

7

6

5

4

3

2

1

0

XXXXXXXX

WRITE

–START DMA INITIATOR RECEIVE

7

6

5

4

3

2

1

0

XXXXXXXX

HT6576A

6

14th July ’97