Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Conditions

Clock Rise and Fall Time

2V

¾¾

2000

ns

5V

¾¾

500

Reset to Clock Setup

2V

¾

4

¾

us

5V

¾

1

¾

Clock to Reset Hold

2V

¾

240

¾

ns

5V

¾

60

¾

Reset Inactive Time

2V

¾

4

¾

us

5V

¾

1

¾

Reset to I/O High Impedance

2V

¾¾

280

ns

5V

¾¾

70

HT1380/HT1381

4

October 2, 1999

Functional Description

The HT1380/HT1381 mainly contains the fol-

lowing internal elements: a data shift register

array to store the clock/calendar data, com-

mand control logic, oscillator circuit and read

timer clock. The clock is contained in eight

read/write registers as shown below. Data con-

tained in the clock register is in binary coded

decimal format.

Two modes are available for transferring the

data between the microprocessor and the

HT1380/HT1381. One is in single-byte mode ad

the other is in multiple-byte mode.

The HT1380/HT1381 also contains two addi-

tional bits, the clock halt bit (CH) and the write

protect bit (WP). These bits control the opera-

tion of the oscillator and so data can be written

to the register array. These two bits should first

be specified in order to read from and write to

the register array properly.

Command byte

For each data transfer, a Command Byte is initiated to specify which register is accessed. This is to

determine whether a read, write, or test cycle is operated and whether a single byte or burst mode

transfer is to occur. Refer to the table shown below and follow the steps to write the data to the chip.

First give a Command Byte of HT1380/HT1381, and then write a data in the register.

This table illustrates the correlation between Command Byte and their bits:

Command Byte

Function Description

C7

C6

C5

C4

C3

C2

C1

C0

Select Read or Write Cycle

R/W

Specify the Register to be Accessed

A2

A1

A0

Clock Halt Flag

C

For IC Test Only

1001

x

x

x

1

Select Single Byte or Burst Mode

1011111

x

Note: ²x² stands for don¢t care