CLC021

SNLS068H – MAY 2000 – REVISED APRIL 2013

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DESCRIPTION (CONTINUED)

Functions performed by the CLC021 include: parallel-to-serial data conversion, ITU-R BT.601-4 input data

parallel data clock frequency multiplication and encoding with the serial data, and differential, serial output data

driving. The CLC021 has circuitry for automatic EDH character and flag generation and insertion per SMPTE RP-

165. The CLC021 has an exclusive built-in self-test (BIST) and video test pattern generator (TPG) with 16

component video test patterns: reference black, PLL and EQ pathologicals and modified colour bars in 4:3 and

16:9 raster formats for NTSC and PAL formats*.

The CLC021 has inputs for enabling sync detection, non-SMPTE mode operation, enabling the EDH function,

NRZ/NRZI mode control and an external reset control. Outputs are provided for H, V and F bits, new TRS sync

character position indication, ancilliary data header detection, NTSC/PAL raster indication and PLL lock detect.

Separate power pins for the output driver, VCO and the serializer improve power supply rejection, output jitter

and noise performance.

The CLC021AVGZ-5.0V is powered by a single +5V supply. The CLC021AVGZ-3.3V is powered by a single

+3.3V supply. Power dissipation is typically 235 mW including two 75

Ω back-matched output loads. The device is

packaged in a JEDEC metric 44-lead PQFP.

BLOCK DIAGRAM

2

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