VIPER25LDTR datasheet(30/40 Pages) STMICROELECTRONICS

No. de pieza	VIPER25LDTR

Descripción Electrónicos	Off-line high voltage converters

PDF	40 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

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30 / 40 page

Operation description

VIPER25

30/40

Doc ID 15585 Rev 4

Equation 11

The RFB(DYN) is the dynamic resistance seen by the FB pin and reported on Table 8 on

page 8

The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB. The

Equation 8 on page 29

can be still used to calculate the OLP delay time but CFB1 has to be

considered instead of CFB. Using the alternative compensation network, the designer can

satisfy, in all case, the loop stability and the enough OLP delay time alike.

Figure 34.

FB pin configuration

Figure 35.

FB pin configuration

()

)

DYN

(

PFB

⋅

From sense FET

4.8V

BURST

PWM

CONTROL

Cfb

To PWM Logic

BURST-MODE

REFERENCES

BURST-MODE

LOGIC

PWM

OLP comparator

To disable logic

4.8V

From sense FET

PWM

CONTROL

PWM

BURST

To disable logic

OLP comparator

To PWM Logic

BURST-MODE

LOGIC

Cfb1

Rfb1

Cfb

BURST-MODE

REFERENCES

VIPER25LDTR Datasheet(PDF) 30 Page - STMicroelectronics

VIPER25LDTR Datasheet(HTML) 30 Page - STMicroelectronics

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