LPC1547JBD48 datasheet(49/99 Pages) NXP

49 / 99 page

LPC15XX

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Product data sheet

Rev. 1 — 19 February 2014

49 of 99

NXP Semiconductors

LPC15xx

32-bit ARM Cortex-M3 microcontroller

8.41 System control

8.41.1 Reset

Reset has four sources on the LPC15xx: the RESET pin, the Watchdog reset, power-on

reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt

trigger input pin. Assertion of chip reset by any source, once the operating voltage attains

a usable level, starts the IRC and initializes the flash controller.

When the internal Reset is removed, the processor begins executing at address 0, which

is initially the Reset vector mapped from the boot block. At that point, all of the processor

and peripheral registers have been initialized to predetermined values.

In Deep power-down mode, an external pull-up resistor is required on the RESET pin.

The RESET pin is operational in active, sleep, deep-sleep, and power-down modes if the

RESET function is selected through the switch matrix for pin PIO0_21 (this is the default).

A LOW-going pulse as short as 50 ns executes the reset and thereby wakes up the part to

its active state. The RESET pin is not functional in Deep power-down mode and must be

pulled HIGH externally while the part is in Deep power-down mode.

8.41.2 Brownout detection

The LPC15xx includes brown-out detection (BOD) with two levels for monitoring the

voltage on the VDD pin. If this voltage falls below one of two selected levels, the BOD

asserts an interrupt signal to the NVIC. This signal can be enabled for interrupt in the

Interrupt Enable Register in the NVIC to cause a CPU interrupt. Alternatively, software can

monitor the signal by reading a dedicated status register. Two threshold levels can be

selected to cause a forced reset of the chip.

8.41.3 Code security (Code Read Protection - CRP)

CRP provides different levels of security in the system so that access to the on-chip flash

and use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be

restricted. Programming a specific pattern into a dedicated flash location invokes CRP.

IAP commands are not affected by the CRP.

Fig 16. RESET pin configuration

LPC1547JBD48 Datasheet(PDF) 49 Page - NXP Semiconductors