CS5101A datasheet(21/40 Pages) CIRRUS

21 / 40 page

ence must supply a maximum load current of

µA peak-to-peak (0.5 µA typical). An output

impedance of 2

Ω will therefore yield a maxi-

mum error of 10.0

µV. With a 4.5 V reference and

LSB size of 138

µV this would insure approxi-

mately 1/14 LSB accuracy. A 10

µF capacitor

exhibits an impedance of less than 2

Ω at fre-

quencies greater than 16 kHz. A high-quality

tantalum capacitor in parallel with a smaller ce-

ramic capacitor is recommended.

Peaking in the reference’s output impedance can

occur because of capacitive loading at its output.

Any peaking that might occur can be reduced by

placing a small resistor in series with the capaci-

tors. The equation in Figure 9 can be used to help

calculate the optimum value of R for a particular

reference. The term "fpeak" is the frequency of

the peak in the output impedance of the reference

before the resistor is added.

The CS5101A and CS5102A can operate with a

wide range of reference voltages, but signal-to-

noise performance is maximized by using as

wide a signal range as possible. The recom-

mended reference voltage is 4.5 volts. The

CS5101A and CS5102A can actually accept ref-

erence voltages up to the positive analog supply.

However, the buffer’s offset may increase as the

reference voltage approaches VA+ thereby in-

creasing external drive requirements at VREF. A

4.5V reference is the maximum reference voltage

recommended. This allows 0.5V headroom for

the internal reference buffer. Also, the buffer en-

lists the aid of an external 0.1

µF ceramic

capacitor which must be tied between its output,

REFBUF, and the negative analog supply, VA-.

For more information on references, consult "Ap-

plication Note: Voltage References for the

CS501X Series of A/D Converters".

Analog Input Connection

The analog input terminal functions similarly to

the VREF input after each conversion when

switching into the track mode. During the first

six master clock cycles in the track mode, the

buffered version of the analog input is used for

coarse-charging the capacitor array. An additional

period is required for fine-charging directly from

AIN to obtain the specified accuracy. Figure 10

shows this operation. During coarse-charge the

charge on the capacitor array first settles to the

buffered version of the analog input. This voltage

may be offset from the actual input voltage. Dur-

ing fine-charge, the charge then settles to the

accurate unbuffered version.

VREF

REFBUF

VA-

0.1

µF

-5V

0.01

µF

+Vee

CS5101A

CS5102A

ref

Figure 9. Reference Connections

π (C1 + C2) fpeak

Acquisition Time (us)

+200

-100

-400

+100

-200

-300

Fine-Charge

Coarse-Charge

0.25

0.5

0.75

1.0

2.0

3.0

4.0

8 MHz Clock

2.0 MHz Clock

Figure 10. Charge Settling Time

(8 and 2.0 MHz Clocks)

CS5101A CS5102A

DS45F2

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