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CS43L41 Datasheet(PDF) 30 Page - Cirrus Logic

No. de pieza CS43L41
Descripción Electrónicos  Low Power 24-Bit, 96 kHz DAC with Volume Control?
PDF  36 Pages
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Fabricante Electrónico  CIRRUS [Cirrus Logic]
Página de inicio  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS43L41 Datasheet(HTML) 30 Page - Cirrus Logic

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CS43L41
30
DS473PP1
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
I2S, Up to 24-Bit data and INT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128I2S, Up to 24-Bit data
and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
I2S, up to 24-Bit DataData Valid on Rising Edge of
SCLK
Figure 20. CS43L41 Format 0 (I2S)
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
I2S, 16-Bit data and INT SCLK = 32 Fs if
MCLK/LRCK = 512, 256 or 128I2S, Up to 24-Bit data
and INT SCLK = 48 Fs if MCLK/LRCK = 384 or 192
I2S, up to 24-Bit DataData Valid on Rising Edge of
SCLK
Figure 21. CS43L41 Format 1 (I2S)
LRCK
SCLK
Left Channel
Right Channel
SDATA
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4 -5
+3 +2 +1 LSB
+5 +4
MSB -1 -2 -3 -4
Internal SCLK Mode
External SCLK Mode
Left Justified, up to 24-Bit DataINT SCLK = 64 Fs if
MCLK/LRCK = 512, 256 or 128INT SCLK = 48 Fs if
MCLK/LRCK = 384 or 192
Left Justified, up to 24-Bit DataData Valid on Rising
Edge of SCLK
Figure 22. CS43L41 Format 2



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