CS4218 datasheet(13/44 Pages) CIRRUS

13 / 44 page

When using the CS4218 as a drop-in replace-

ment for the CS4216, the external 600 ohm

series resistors on LOUT and ROUT are not re-

quired, since they are part of the CS4218

internal circuitry.

In applications where both CS4218 and CS4216

are to be used, a board stuff option should be

included in the bill of materials which will allow

either a 600-ohm or a 0-ohm resistor to be used

externally on both LOUT and ROUT.

Offset Calibration

Both input and output offset voltages are mini-

mized by internal calibration. Offset calibration

occurs after exiting a reset or power down condi-

tion. During calibration, which takes 194 frames,

output data from the ADCs will be all zeros, and

will be flagged as invalid. Also, the DAC out-

puts will be muted. After power down mode or

power up,

RESET should be held low for a

minimum of 50 ms to allow the voltage refer-

ence to settle. Changing sample rates in master

and slave modes automatically initiates a calibra-

tion.

Input Gain and Output Level Setting

Input gain is adjustable from 0 dB to +22.5 dB

in 1.5 dB steps. Output level attenuation is ad-

justable from 0 dB to -46.5 dB in 1.5 dB steps.

Both input and output gain adjustments are inter-

nally made on zero-crossings of the analog

signal, to minimize "zipper" noise. The gain

change automatically takes effect if a zero cross-

ing does not occur within 512 frames.

Muting and the ADC Valid Counter

The mute function allows the the user to turn off

the output channels ( LOUT and ROUT ). Prior

to muting, the attenuation should be gradually

ramped to maximum ( 46.5 dB ), taking 1.5dB

steps. This significantly reduces any audible arti-

facts that may be heard once muting is enabled.

It is the users responsibility to program the serial

host to perform the ramping.

The serial data stream contains a "Valid Data"

indicator, the ADV bit, for the A/D converters

which is low until enough clocks have passed

since reset, or low-power (power down mode)

operation to have valid A/D data from the filters

(i.e., until calibration time plus the full latency

of the digital filters has passed.)

Parallel Digital Input/Output Pins

Parallel digital inputs are general purpose pins

whose values are reflected in the serial data out-

put stream to the processor. Parallel digital

outputs provide a way to control external devices

using bits in the serial data input stream. All par-

allel digital pins, with the exception of DI1 and

DO1, are multifunction and are defined by the

serial mode selected. In Serial Mode 3 master

modes and Serial Mode 5, two digital inputs and

two digital outputs are available. In Serial Mode

3 slave modes, three digital inputs and two digi-

tal outputs are available. In Serial Mode 4 only

one digital input and digital output exists. Fig-

ure 10 shows when the DI pins are latched, and

when the DO pins are updated.

Reset and Power Down Modes

Reset places the CS4218 into a known state and

must be held low for at least 50 ms after power-

up or a hard power down. In reset, the digital

outputs are driven low. Reset sets all control data

SSYNC

SCLK

DI pins

latched

DO pins

update

Start of

Frame

(SM3)

Figure 10. Digital Input/Output Timing

CS4218

DS135F1

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