SN54LS259 datasheet(2/6 Pages) MOTOROLA

2 / 6 page

MODE

Addressable Latch

Memory

Active HIGH Eight-Channel

Demultiplexer

Clear

MODE SELECTION

X = Don’t Care Condition

L = LOW Voltage Level

H = HIGH Voltage Level

QN–1 = Previous Output State

5-434

FAST AND LS TTL DATA

SN54/74LS259

LOGIC DIAGRAM

A1 A2

VCC = PIN 16

GND = PIN 8

= PIN NUMBERS

FUNCTIONAL DESCRIPTION

The SN54 / 74LS259 has four modes of operation as shown

in the mode selection table. In the addressable latch mode,

data on the Data line (D) is written into the addressed

latch.The addressed latch will follow the data input with all

non-addressed latches remaining in their previous states. In

the memory mode, all latches remain in their previous state

and are unaffected by the Data or Address inputs.

In the one-of-eight decoding or demultiplexing mode, the

addressed output will follow the state of the D input with all

other inputs in the LOW state. In the clear mode all outputs are

LOW and unaffected by the address and data inputs.

When operating the SN54 / 74LS259 as an addressable

latch, changing more then one bit of the address could impose

a transient wrong address. Therefore, this should only be

done while in the memory mode.

The truth table below summarizes the operations.

TRUTH TABLE

PRESENT OUTPUT STATES

C E D A0 A1 A2

MODE

L H X

Clear

L L L

Demultiplex

L L H

L L L

L L H

• • •

•

• • •

•

• • •

•

• • •

•

• • •

•

L L H

H H X

QN–1

Memory

H I

QN–1 QN–1 QN–1

Addressable

H L H

QN–1 QN–1

Latch

H L L

QN–1

H L H

QN–1

• • •

•

• • •

•

• • •

•

• • •

•

• • •

•

H L L

QN–1

H L H

QN–1

SN54LS259 Datasheet(PDF) 2 Page - Motorola, Inc

SN54LS259 Datasheet(HTML) 2 Page - Motorola, Inc

Html Pages

1 2 3 4 5 6

Datasheet Descarga

Enlace URL