AT24CS128/256

4

Notes:

1. This parameter is characterized and is not 100% tested.

2. AC measurement conditions:

R

Input pulse voltages: 0.3V

Input rise and fall times:

≤50ns

Input and output timing reference voltages: 0.5V

CC

Device Operation

CLOCK and DATA TRANSITIONS: The SDA pin is nor-

mally pulled high with an external device. Data on the SDA

pin may change only during SCL low time periods (refer to

Data Validity timing diagram). Data changes during SCL

high periods will indicate a start or stop condition as defined

below.

START CONDITION: A high-to-low transition of SDA with

SCL high is a start condition which must precede any other

command (refer to Start and Stop Definition timing dia-

gram).

STOP CONDITION: A low-to-high transition of SDA with

SCL high is a stop condition. After a read sequence, the

stop command will place the EEPROM in a standby power

mode (refer to Start and Stop Definition timing diagram).

ACKNOWLEDGE: All addresses and data words are seri-

ally transmitted to and from the EEPROM in 8-bit words.

The EEPROM sends a zero during the ninth clock cycle to

acknowledge that it has received each word.

STANDBY MODE: The AT24CS128/256 features a low

power standby mode which is enabled: a) upon power-up

and b) after the receipt of the STOP bit and the completion

of any internal operations.

MEMORY RESET: After an interruption in protocol, power

loss or system reset, any 2-wire part can be reset by follow-

ing these steps: (a) Clock up to 9 cycles, (b) look for SDA

high in each cycle while SCL is high and then (c) create a

start condition as SDA is high.

AC Characteristics

Applicable over recommended operating range from T

erwise noted). Test conditions are listed in Note 2.

Symbol

Parameter

1.8-volt

2.7-volt

5.0-volt

Units

MinMax

MinMax

MinMax

f

SCL

Clock Frequency, SCL

400

1000

1000

kHz

t

LOW

Clock Pulse Width Low

1.3

0.6

0.6

µs

t

HIGH

Clock Pulse Width High

1.0

0.4

0.4

µs

t

AA

Clock Low to Data Out Valid

0.1

0.9

0.05

0.55

0.05

0.55

µs

t

BUF

Time the bus must be free before a new

1.2

0.5

0.5

µs

t

HD.STA

Start Hold Time

0.6

0.25

0.25

µs

t

SU.STA

Start Set-up Time

0.6

0.25

0.25

µs

t

HD.DAT

Data In Hold Time

0

0

0

µs

t

SU.DAT

Data In Set-up Time

100

100

100

ns

t

R

0.3

0.3

0.3

µs

t

F

300

100

100

ns

t

SU.STO

Stop Set-up Time

0.6

0.25

0.25

µs

t

DH

Data Out Hold Time

50

50

50

ns

t

WR

Write Cycle Time

20

10

10

ms

5.0V, 25°C, Page Mode

100K

100K

100K

Write

Cycles