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AS8650B

Datasheet - Detailed Descr i p ti on

7.3 State Diagram

Figure 5. State Machine Model

7.4 Initialization Sequence

The DCDC converter is switched ‘ON’. Subsequently, on receiving power-good (PG) signal from the DCDC converter, the LDO1 regulator is

switched ‘ON’. During the initialization sequence, the VLDO1 is set to 2.5V if VLDO1 > VLDO1_POKTH threshold. VLDO1_RESET is released to

‘high’. Then, active-low PORN_2_OTP is generated.

Initially the rising edge of PORN_2_OTP loads contents into the OTP latch. Next the LOAD_OTP_IN_PREREG signal loads the content of OTP

latch into the pre-regulator domain register. Once the VLDO1_POKTH threshold is reached, the reset timeout timer also starts.

microcontroller generates a trigger within the startup window, then the device enters into Standby mode.

If the microcontroller fails to generate the trigger, then the RESET signal is generated and the Reset timeout will start.

If the microcontroller fails to generate the startup watchdog trigger for 3 consecutive times, then the device enters into Sleep mode. On receiving

Normal mode command from the microcontroller, the LDO2 and LDO3 regulators are activated. By the time VLDO2 and VLDO3 reach their

respective power-ok (POK) threshold values, an interrupt signal is generated. The AS8650B supports very slow VSUP ramp up of 0.5V/min.

Power Off

Normal

Receive Only

Standby

Sleep

Host command (go to ReceiveOnly)

Host command (go to Normal)

Hos

t co

mm

and

(go

to N

orm

al)

Hos

t co

mm

and

(go

to S

tand

by)

BUS Wake

OR

Local Wake

Host command (go to Sleep)

Hos

t co

mm

and

(go

to S

leep

)

disabled

disabled BUS transmitter will be

From any state

Power-up

VS

UP

_P

OR

_R

ES

ET

==

0

VLDO

1 PO

R tim

eout

OR

startup

watch

dog tim

eout

Standby state

VSUP_UV_flag = 1 OR V5V_UV_flag =1

VSUP_UV_flag =1 OR

V5V_UV_flag= 1

transceiver disabled