CD54HC160, CD54HC162

BCD SYNCHRONOUS DECADE COUNTERS

SCHS301 – JUNE 2000

5

POST OFFICE BOX 655303

typical clear, preset, count, and inhibit sequences

Illustrated below is the following sequence:

1.

Clear outputs to zero (CD54HC160 is asynchronous; CD54HC162 is synchronous)

2.

Preset BCD to seven

3.

Count to eight, nine, zero, one, two, and three

4.

Inhibit

0

Async

Clear

3

2

1

9

8

7

Preset

Sync

Clear

Outputs

Data

Inputs

RCO

QD

QC

QB

QA

ENT

ENP

CLK

D

C

B

A

LOAD

CLR

Inhibit

Count

CD54HC160, CD54HC162