2.7V to 3.6V and 4.5V to 5.5V, Low-Power,

4-/12-Channel, 2-Wire Serial, 12-Bit ADCs

14

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BIT 7

(MSB)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

(LSB)

REG

SCAN1

SCAN0

CS3

CS2

CS1

CS0

SGL/DIF

BIT

NAME

DESCRIPTION

7

REG

Register bit 1 = setup byte (see Table 1), 0 = configuration byte.

6

SCAN1

5

SCAN0

Scan select bits. Two bits select the scanning configuration (Table 5). Default to 00 at power-up.

4

CS3

3

CS2

2

CS1

1

CS0

Channel select bits. Four bits select which analog input channels are to be used for conversion

(Tables 3 and 4). Default to 0000 at power-up. For MAX1236/MAX1237, CS3 and CS2 are

internally set to 0.

0

SGL/DIF

1 = single-ended, 0 = differential (Tables 3 and 4). Default to 1 at power-up. See the Single-

Ended/Differential Input section.

Table 2. Configuration Byte Format

CS3

1

CS2

1

CS1

CS0

AIN0

AIN1

AIN2

AIN3

2

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10 AIN11

2

GND

0

000

+

-

0

001

+

-

0

010

+

-

0

011

+

-

0

100

+

-

0

101

+

-

0

110

+

-

0

111

+

-

1

000

+

-

1

001

+-

1

010

+-

1

011

+

-

1

1

0

0

RESERVED

1

1

0

1

RESERVED

1

1

1

0

RESERVED

1

1

1

1

RESERVED

1. For MAX1236/MAX1237, CS3 and CS2 are internally set to 0.

2. When SEL1 = 1, a single-ended read of AIN3/REF (MAX1236/MAX1237) or AIN11/REF (MAX1238/MAX1239) is ignored; scan

stops at AIN2 or AIN10.

Table 3. Channel Selection in Single-Ended Mode (SGL/DIF = 1)