IO96NDB2V1 datasheet(136/242 Pages) MICROSEMI

No. de pieza	IO96NDB2V1

Descripción Electrónicos	ProASIC3L Low Power Flash FPGAs with Flash*Freeze Technology

PDF	242 Pages

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Fabricante Electrónico	MICROSEMI [Microsemi Corporation]

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ProASIC3L DC and Switching Characteristics

2-120

Revision 13

1.2 V DC Core Voltage

Table 2-199 • Output DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V

Parameter

Description

–1

Std.

Units

tDDROCLKQ

Clock-to-Out of DDR for Output DDR

1.10

0.94

tDDRISUD1

Data_F Data Setup for Output DDR

0.59

0.50

tDDROSUD2

Data_R Data Setup for Output DDR

0.59

0.50

tDDROHD1

Data_F Data Hold for Output DDR

0.00

tDDROHD2

Data_R Data Hold for Output DDR

0.00

tDDROCLR2Q

Asynchronous Clear-to-Out for Output DDR

1.26

1.07

tDDROREMCLR

Asynchronous Clear Removal Time for Output DDR

0.00

tDDRORECCLR

Asynchronous Clear Recovery Time for Output DDR

0.35

0.30

tDDROWCLR1

Asynchronous Clear Minimum Pulse Width for Output DDR

0.22

0.19

tDDROCKMPWH

Clock Minimum Pulse Width High for the Output DDR

0.36

0.31

tDDROCKMPWL

Clock Minimum Pulse Width Low for the Output DDR

0.32

0.28

FDDOMAX

Maximum Frequency for the Output DDR

160.00 160.00

MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.

IO96NDB2V1 Datasheet(PDF) 136 Page - Microsemi Corporation

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