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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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AM79C971VCW Datasheet(PDF) 262 Page - Advanced Micro Devices |
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AM79C971VCW Datasheet(HTML) 262 Page - Advanced Micro Devices |
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262 / 265 page  I-4 External SRAM Configuration 90 F FIFO DMA Transfers 50 Framing Transmit and Receive Message Data Encapsulation 60 Frequency Demands for Network Operation Expansion Bus Interface 94 Full-Duplex Link Status LED Support 76 Operation 75 Functions Basic 29 Detailed 30 G General Description 2 General Purpose Serial Interface 75 I I/O Resources 103 IEEE 1149.1 (1990) Test Access Port Interface Boundary Scan Register 99 Instruction Register and Decoding Logic 99 Other Data Registers 100 Supported Instructions 99 TAP Finite State Machine 99 Initialization Buffer Management Unit 53 Initialization Block Description 180 DMA Transfers 47 LADRF 182 Mode 183 PADR 182 RDRA and TDRA 181 RLEN and TLEN 181 Input Signal Conditioning, MENDEC 71 Instruction Register and Decoding Logic 99 J Jabber Function, Twisted Pair Transceiver 74 L LADRF 182 LAPP Flow, Outline of D-1 LAPP Setup D-1 Late Collision 65 LED Support 97 Link Test Function, Twisted Pair Transceiver 73 Look-Ahead Packet Processing (LAPP) Concept D-1 Loopback Features Media Independent Interface 69 Miscellaneous 69 Loss of Carrier 65 Low Latency Receive Configuration 92 M MAC 60, 61, 62 Magic Packet Mode, Power Saving 97, 98 Manchester Encoder/Decoder 70 Carrier Tracking and End of Message 71 Clock Acquisition 71 Data Decoding 72 External Clock Drive Characteristics 70 External Crystal Characteristics 70 Input Signal Conditioning 71 Jitter Tolerance Definition 72 MENDEC Transmit Path 70 PLL Tracking 71 Receiver Path 71 Transmitter Timing and Operation 70 Manufacturer Contact Information A-2 Master Abort 43 Master Bus Interface Unit 36 Bus Acquisition 36 Bus Master DMA Transfers 37 Basic Burst Read Transfer 37 Basic Burst Write Transfer 39 Basic Non-Burst Write Transfer 39 Burst FIFO DMA Transfers 52 Descriptor DMA Transfers 47 Disconnect With Data Transfer 40 Disconnect Without Data Transfer 41 FIFO DMA Transfers 50 Initialization Block DMA Transfers 47 Master Abort 43 Master Initiated Termination 42 Non-Burst FIFO DMA Transfers 50 Parity Error Response 43 Preemption During Burst Transaction 42 Preemption During Non-Burst Transaction 42 Master Initiated Termination 42 Media Access Control 60 Collision Handling 63 Destination Address Handling 61 Error Detection 61 Framing 60 Management 61 Medium Allocation 62 Transmit and Receive Message Data Encapsulation 60 Media Independent Interface Auto-Poll External PHY Status Polling 78 Described 76 Loopback Features 69 Medium Allocation 62 MII Management Frames 78 |
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