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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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AM79C971VCW Datasheet(PDF) 261 Page - Advanced Micro Devices |
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AM79C971VCW Datasheet(HTML) 261 Page - Advanced Micro Devices |
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261 / 265 page  I-3 Current Transmit Byte Count 137 CSR43 Current Transmit Status 137 CSR44 Next Receive Byte Count 137 CSR45 Next Receive Status 137 CSR46 Transmit Poll Time Counter 137 CSR47 Transmit Polling Interval 137 CSR48 Receive Poll Time Counter 138 CSR49 Receive Polling Interval 138 CSR5 Extended Control and Interrupt 1 123 CSR58 Software Style 139 CSR6 RX/TX Descriptor Table Length 125 CSR60 Previous Transmit Descriptor Address Lower 140 CSR61 Previous Transmit Descriptor Address Upper 140 CSR62 Previous Transmit Byte Count 141 CSR63 Previous Transmit Status 141 CSR64 Next Transmit Buffer Address Lower 141 CSR65 Next Transmit Buffer Address Upper 141 CSR66 Next Transmit Byte Count 141 CSR67 Next Transmit Status 141 CSR7 Extended Control and Interrupt 2 126 CSR72 Receive Ring Counter 142 CSR74 Transmit Ring Counter 142 CSR76 Receive Ring Length 142 CSR78 Transmit Ring Length 142 CSR8 Logical Address Filter 0 129 CSR80 DMA Transfer Counter and FIFO Threshold Control 142 CSR82 Transmit Descriptor Address Pointer Lower 144 CSR84 DMA Address Register Lower 145 CSR86 Buffer Byte Counter 145 CSR88 Chip ID Register Lower 145 CSR89 Chip ID Register Upper 146 CSR9 Logical Address Filter 1 129 CSR92 Ring Length Conversion 146 D Data Decoding 72 Data Registers, Other 100 DC Characteristics, Over Commercial Operating Ranges Unless Otherwise Specified 200 Decoupling/Bypass Capacitors B-1 Descriptor DMA Transfers 47 Rings 54 Detailed Functions 30 Differential Input Termination 72 Direct Access to the Interface 95 Direct Flash Access 86 Direct SRAM Access 92 Disconnect Of Burst Transfer 34 Without Data Transfer 41 Distinctive Characteristics 1 DMA Transfers FIFO 50 E EEPROM Interface 22, 94 EEPROM MAP 95 EEPROM-Programmable Registers 95 Expansion Bus Interface 22, 84 AMD Flash Programming 89 Direct Flash Access 86 Direct SRAM Access 92 Expansion ROM - Boot Device Access 84 External SRAM Configuration 90 Frequency Demands for Network Operation 94 Low Latency Receive Configuration 92 No SRAM Configuration 92 SRAM Accesses 93 SRAM Interface Bandwidth Requirements 94 Expansion ROM - Boot Device Access 84 Expansion ROM Transfers 33 External Address Detection Interface 81 Internal PHY 81 Receive Frame Tagging 83 External Address Detection Interface, EEPROM Interface 26 |
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