AM79C971VCW datasheet(245/265 Pages) AMD

245 / 265 page

Am79C971

D-9

Figure D3.

LAPP Timeline for Two-Interrupt Method

Buffer

Ethernet

Controller

activity:

Software

activity:

Buffer

S0: Driver is idle.

C1: Controller is performing intermittent

bursts of DMA to fill data buffer #1.

Ethernet

Wire

activity:

N0: Packet preamble, SFD

and destination address

are arriving.

C3: SRP interrupt

is generated.

C5: Controller is performing intermittent

bursts of DMA to fill data buffer #2.

S1: Interrupt latency.

S3: Driver writes modified application

pointer to descriptor #3.

C8: Controller is performing intermittent

bursts of DMA to fill data buffer #3.

N1: 64th byte of packet

data arrives.

S4: Driver copies data from buffer #1 to the application buffer.

S5: Driver polls descriptor #2.

S7: Driver polls descriptor of buffer #3.

S8: Driver calls application

to tell application that

packet has arrived.

S6: Driver copies data from buffer #2 to the application buffer.

C9: Controller writes descriptor #3.

C0: Lookahead to descriptor #2.

C2: Controller writes descriptor #1.

S2: Driver call to application to

get application buffer pointer.

{

S9: Application processes packet, generates TX packet.

S10: Driver sets up TX descriptor.

C4: Lookahead to descriptor #3 (OWN).

C6: "Last chance" lookahead to

descriptor #3 (OWN).

C7: Controller writes descriptor #2.

}

}{

{

N2: EOM

19364D-D3

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