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A3P030 Datasheet(PDF) 109 Page - Microsemi Corporation |
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A3P030 Datasheet(HTML) 109 Page - Microsemi Corporation |
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109 / 220 page ![]() ProASIC3 Flash Family FPGAs Revision 13 2-95 tRECRSTB RESET recovery 1.50 1.71 2.01 ns tMPWRSTB RESET minimum pulse width 0.21 0.24 0.29 ns tCYC Clock cycle time 3.23 3.68 4.32 ns FMAX Maximum frequency 310 272 231 MHz Table 2-116 • RAM4K9 Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V (continued) Parameter Description –2 –1 Std. Units Notes: 1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash- Based cSoCs and FPGAs. 2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values. |
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