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A3P030 Datasheet(PDF) 82 Page - Microsemi Corporation |
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A3P030 Datasheet(HTML) 82 Page - Microsemi Corporation |
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82 / 220 page ![]() ProASIC3 DC and Switching Characteristics 2-68 Revision 13 I/O Register Specifications Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Preset Figure 2-14 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset INBUF INBUF CLKBUF Data Input I/O Register with: Active High Enable Active High Preset Positive-Edge Triggered Data Output Register and Enable Output Register with: Active High Enable Active High Preset Postive-Edge Triggered CLK Enable Preset Data_out Data EOUT DOUT DQ DFN1E1P1 PRE DQ DFN1E1P1 PRE DQ DFN1E1P1 PRE A B C D E E E E F G H I J L K Y Core Array |
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