MP2932 - 6-PHASE PWM CONTROLLER WITH 8-BIT ADC CODE

MP2932 Rev.1.02

www.MonolithicPower.com

11

4/30/2012

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© 2012 MPS. All Rights Reserved.

If the RC network components are selected

such that the RC time constant (=R*C) matches

the inductor time constant (=L/DCR), the

voltage drop across the DCR, i.e., proportional

to the channel current.

proportional to the inductor current and it can

be seen form Equation (4).

ISEN

R

DCR

L

I

SEN

I





(4)

Resistive Sensing

For accurate current sense, a current-sense

inductor can also be adopted (see Figure 3).

This technique reduces overall converter

efficiency due to the additional power loss on

Equation (5) shows the relationship between

ISEN

R

SENSE

R

L

I

SEN

I





(5)

CURRENT

SENSE

I

ISEN+(n)

ISEN-(n)

MP2932 INTERNAL CIRCUIT

L

n

=I

R

R

SEN

I

L

SENSE

ISEN

Figure 3—Sense Resistor in Series with

Inductors

Channel-Current Balance

The sensed current from each active channel is

summed together and divided by the number of

active channels. The resulting average current

current. Channel current balance is achieved by

comparing the sensed current of each channel

to the average current to make an appropriate

adjustment to the PWM duty cycle of each

channel.

Output Voltage and Load-Line Regulation

The MP2932 uses an internal differential

remote-sense amplifier as shown in Figure 4.

The microprocessor voltage is sensed between

the VSEN and RGND pins.

compared to sawtooth waveforms to generate

the PWM signals. The typical open-loop gain of

error amplifier is no less than 80dB, and the

typical open-loop bandwidth is no less than

20MHz. The PWM signals control the timing of

the

MPS

Intelli-phase

and

regulate

the

converter output to the specified reference

voltage.

R

C

R

C

MP2932 INTERNAL CIRCUIT

FB

ERROR AMPLIFIER

IDROOP

VDIFF

VSEN

RGND

DIFFERENTIAL

REMOTE-SENSE

AMPLIFIER

V

I

REF

DAC

COMP

EXTERNAL CIRCUIT

R

V

REF

REF

FB

DROOP

C

C

COMP

AVG

Figure 4—Output Voltage and Load-line

Regulation

connected between FB pin and the remote

sense output (VDIFF). As shown in Figure 4,

flows from FB through the load-line regulation

FB

R

AVG

I

DROOP

V



(6)

The output voltage is reduced by the droop

current. It’s derived by combining Equation (6)

with the appropriate sensing current expression

defined by the current sense method.