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APA600 Datasheet(PDF) 65 Page - Actel Corporation

No. de pieza APA600
Descripción Electrónicos  ProASICPLUS짰 Flash Family FPGAs
PDF  178 Pages
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Fabricante Electrónico  ACTEL [Actel Corporation]
Página de inicio  http://www.actel.com
Logo ACTEL - Actel Corporation

APA600 Datasheet(HTML) 65 Page - Actel Corporation

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ProASICPLUS Flash Family FPGAs
v5.9
2-55
Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
Note: The plot shows the normal operation status.
Figure 2-28 • Synchronous SRAM Read, Access Timed Output Strobe (Synchronous Transparent)
Table 2-52 • TJ = 0°C to 110°C; VDD = 2.3 V to 2.7 V for Commercial/Industrial
TJ = –55°C to 150°C, VDD = 2.3 V to 2.7 V for Military/MIL-STD-883
Symbol txxx
Description
Min.
Max.
Units
Notes
CCYC
Cycle time
7.5
ns
CMH
Clock high phase
3.0
ns
CML
Clock low phase
3.0
ns
OCA
New DO access from RCLKS
↑
7.5
ns
OCH
Old DO valid from RCLKS
↑
3.0
ns
RACH
RADDR hold from RCLKS
↑
0.5
ns
RACS
RADDR setup to RCLKS
↑
1.0
ns
RDCH
RDB hold from RCLKS
↑
0.5
ns
RDCS
RDB setup to RCLKS
↑
1.0
ns
RPCA
New RPE access from RCLKS
↑
9.5
ns
RPCH
Old RPE valid from RCLKS
↑
3.0
ns
RADDR
RPE
DO
RCLKS
RBD, RBLKB
New Valid Data Out
Cycle Start
Old Data Out
New Valid
Address
tRACS
tRDCS
tRDCH
tRACH
tOCH
tRPCH
tCMH
tOCA
tRPCA
tCCYC
tCML



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