AD7948ARS-B datasheet(5/16 Pages) AD

5 / 16 page

AD7943/AD7945/AD7948

REV. B

–5–

(TA = TMIN to TMAX, unless otherwise noted)

Limit @

Parameter

VDD = +3 V to +3.6 V

VDD = +4.5 V to +5.5 V

Units

Description

tSTB

ns min

STB Pulsewidth

tDS

ns min

Data Setup Time

tDH

ns min

Data Hold Time

tSRI

ns min

SRI Data Pulsewidth

tLD

ns min

Load Pulsewidth

tCLR

ns min

CLR Pulsewidth

tASB

ns min

Min Time Between Strobing Input Shift

tSV

ns max

STB Clocking Edge to SRO Data Valid Delay

NOTES

1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1

µs on any digital input.

2STB mark/space ratio range is 60/40 to 40/60.

SV is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.

Specifications subject to change without notice.

tSTB

STB1,

STB2,

STB4

STB3

tDS

tDH

tSRI

SRI

DB11(N)

(MSB)

DB10(N)

DB0(N)

DB0(N–1)

DB10(N–1)

LD1,

LD2,

CLR

SRO

tSV

tLD, tCLR

tASB

Figure 1. AD7943 Timing Diagram

TO OUTPUT

50pF

1.6mA

IOL

+2.1V

IOH

200 A

Figure 2. Load Circuit for Digital Output Timing Specifications

AD7943 TIMING SPECIFICATIONS1

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