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AD1835AAS Datasheet(PDF) 5 Page - Analog Devices

No. de pieza AD1835AAS
Descripción Electrónicos  2 ADC, 8 DAC, 96 kHz, 24-Bit Codecs
PDF  24 Pages
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD1835AAS Datasheet(HTML) 5 Page - Analog Devices

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REV. A
AD1835A
–5–
Parameter
Min
Max
Unit
Comments
TDM256 MODE (Master, 48 kHz and 96 kHz)
tTBD
BCLK Delay
40
ns
From MCLK Rising
tFSD
FSTDM Delay
5
ns
From BCLK Rising
tTABDD
ASDATA Delay
10
ns
From BCLK Rising
tTDDS
DSDATA1 Setup
15
ns
To BCLK Falling
tTDDH
DSDATA1 Hold
15
ns
From BCLK Falling
TDM256 MODE (Slave, 48 kHz and 96 kHz)
fAB
BCLK Frequency
256
fS
tTBCH
BCLK High
17
ns
tTBCL
BCLK Low
17
ns
tTFS
FSTDM Setup
10
ns
To BCLK Falling
tTFH
FSTDM Hold
10
ns
From BCLK Falling
tTBDD
ASDATA Delay
15
ns
From BCLK Rising
tTDDS
DSDATA1 Setup
15
ns
To BCLK Falling
tTDDH
DSDATA1 Hold
15
ns
From BCLK Falling
TDM512 MODE (Master, 48 kHz)
tTBD
BCLK Delay
40
ns
From MCLK Rising
tFSD
FSTDM Delay
5
ns
From BCLK Rising
tTABDD
ASDATA Delay
10
ns
From BCLK Rising
tTDDS
DSDATA1 Setup
15
ns
To BCLK Falling
tTDDH
DSDATA1 Hold
15
ns
From BCLK Falling
TDM512 MODE (Slave, 48 kHz )
fAB
BCLK Frequency
512
fS
tTBCH
BCLK High
17
ns
tTBCL
BCLK Low
17
ns
tTFS
FSTDM Setup
10
ns
To BCLK Falling
tTFH
FSTDM Hold
10
ns
From BCLK Falling
tTBDD
ASDATA Delay
15
ns
From BCLK Rising
tTDDS
DSDATA1 Setup
15
ns
To BCLK Falling
tTDDH
DSDATA1 Hold
15
ns
From BCLK Falling
AUXILIARY INTERFACE (48 kHz and 96 kHz)
tAXDS
AAUXDATA Setup
10
ns
To AUXBCLK Rising
tAXDH
AAUXDATA Hold
10
ns
From AUXBCLK Rising
fABP
AUXBCLK Frequency
64
fS
Slave Mode
tAXBH
AUXBCLK High
15
ns
tAXBL
AUXBCLK Low
15
ns
tAXLS
AUXLRCLK Setup
10
ns
To AUXBCLK Rising
tAXLH
AUXLRCLK Hold
10
ns
From AUXBCLK Rising
Master Mode
tAUXLRCLK
AUXLRCLK Delay
15
ns
From AUXBCLK Falling
tAUXBCLK
AUXBCLK Delay
20
ns
From MCLK Rising
Specifications subject to change without notice.
MCLK
t
MH
PD/RST
t
ML
t
PDR
t
MCLK
Figure 1. MCLK and
PD/ RST Timing



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