TLC7524C, TLC7524E, TLC7524I

8BIT MULTIPLYING DIGITALTOANALOG CONVERTERS

SLAS061D − SEPTEMBER 1986 − REVISED JUNE 2007

4

POST OFFICE BOX 655303

OUT1 and OUT2 at GND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VDD = 5V

VDD = 15V

UNIT

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

MIN

TYP

MAX

UNIT

Linearity error

±0.5

±0.5

LSB

Gain error

See Note 1

±2.5

±2.5

LSB

Settling time (to 1/2 LSB)

See Note 2

100

100

ns

Propagation delay from digital input

to 90% of final analog output current

See Note 2

80

80

ns

Feedthrough at OUT1 or OUT2

Vref =

±10V (100kHz sinewave)

WR and CS at 0V, DB0−DB7 at 0V

0.5

0.5

%FSR

Temperature coefficient of gain

TA = +25°C to MAX

±0.004

±0.001

%FSR/

°C

NOTES:

1. Gain error is measured using the internal feedback resistor. Nominal full-scale range (FSR) = Vref − 1LSB.

2. OUT1 load = 100

Ω, Cext = 13pF, WR at 0V, CS at 0V, DB0 − DB7 at 0V to VDD or VDD to 0V.

operating sequence

DB0−DB7

WR

CS

th(D)

tsu(D)

tw(WR)

th(CS)

tsu(CS)