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DM7300 Datasheet(PDF) 6 Page - Power-One |
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DM7300 Datasheet(HTML) 6 Page - Power-One |
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6 / 36 page  ZD-00896 Rev. 5.2, 9-Apr-13 www.power-one.com Page 6 of 36 8.3 Signal Specifications Parameter Conditions/Description Min Nom Max Units SYNC/DATA Line SDpu SD pull up resistor 5 k SDthrL SD input low voltage threshold 0.31·VDD 0.52·VDD V SDthrH SD input high voltage threshold 0.45·VDD 0.81·VDD V SDhys SD input hysteresis 0.37 1.1 V SDsink SD sink capability (VSD=0.5V) 30 mA Freq_sd Clock frequency 450 550 kHz Tsynq Sync pulse duration 22 28 % of clock cycle T0 Data=0 pulse duration 72 78 % of clock cycle Interrupt Inputs (INT_N[3:0]) Rpu3 Pull up resistor 30 k VthrL3 Input low voltage threshold 0.31·VDD 0.52·VDD V VthrH3 Input high voltage threshold 0.45·VDD 0.81·VDD V Vhys3 Input hysteresis 0.37 1.1 V ADDR[3:0], ACFAIL_N, RES_N, LCK_N, PG[3:0] Inputs Rpu1 Pull up resistor 20 50 k VthrL1 Input low voltage -0.5 0.2·VDD V VthrH1 Input high voltage 0.7·VDD VDD+0.5 V HRES_N Input Rpu2 HRES_N pull up resistor (with series diode, see note 1) 30 60 k VthrL2 HRES_N input low voltage -0.5 0.2·VDD V VthrH2 HRES_N input high voltage 0.9·VDD VDD+0.5 V Inputs/Outputs (OK_A, OK_B, OK_C, OK_D) OKpu OK pull up resistor 5 k OKthrL OK input low voltage threshold 0.31·VDD 0.52·VDD V OKthrH OK input high voltage threshold 0.45·VDD 0.81·VDD V OKhys OK input hysteresis 0.37 1.1 V OKsink OK sink capability (VOK=0.5V) 30 mA Enable Outputs (EN[3:0]) VEN EN logic level enabled High VEN EN logic level disabled Low VENH EN output high voltage IOH = -10 mA VDD-0.6 V VENL EN output low voltage IOL = 5 mA 0.5 V ______________________________________ 1 HRES_N Input - Because the input does not have an internal ESD protection diode connected to VDD, the user needs to add an external diode between the HRES_N and VDD pins as shown in Figure 3. |
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