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PCF8564AU/5GC/1 Datasheet(PDF) 4 Page - NXP Semiconductors |
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PCF8564AU/5GC/1 Datasheet(HTML) 4 Page - NXP Semiconductors |
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4 / 48 page  PCF8564A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved. Product data sheet Rev. 3 — 26 August 2013 4 of 48 NXP Semiconductors PCF8564A Real time clock and calendar 7. Pinning information 7.1 Pinning 7.2 Pin description [1] The substrate (rear side of the die) is at VSS potential and must not be connected. Viewed from active side. For mechanical details, see Figure 27 and Figure 28. Fig 2. Pinning diagram of PCF8564A Table 4. Pin description Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified. Symbol Pin Description OSCI 1 oscillator input OSCO 2 oscillator output INT 3 interrupt output, open-drain, active LOW VSS 4 ground[1] SDA 5 serial data input and output SCL 6 serial clock input CLKOUT 7 clock output, push-pull VDD 8 supply voltage CLKOE 9 CLKOUT enable input |
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