STLUX385ATR datasheet(34/99 Pages) STMICROELECTRONICS

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I/O multifunction signal configuration

STLUX385A

34/98

DocID024387 Rev 2

5.4.1

P2 programmable pull-up feature

The pad pull-up resistances (47 k

Ω) of Port2 signals are individually controllable by

MSC_INPP2AUX1 register.

5.5

Multifunction Port configuration registers

MSC_IOMXP0 (Port P1 I/O mux control register)

Port0 I/O multifunction signal configurations register (for functionality description refers to

Section 5.2).

Bit 1-0:

Sel_p010[1:0] Port0[1:0] I/O multiplexing scheme:

00: Port0[1:0] are interconnected to GPIO0[1:0] signals

01: Port0[1:0] are interconnected to UART_rx and UART_tx signals

10: Port0[1:0] are interconnected to I

C_scl and I

C_sda signals

11: RFU

Bit 3-2:

Sel_p032[1:0] Port0[3:2] I/O multiplexing scheme:

00: Port0[3:2] are interconnected to GPIO0[3:2] signals

01: Port0[3:2] are interconnected to I

C_scl and I

C_sda signals

10: Port0[3:2] are interconnected to HseOscin and HseOscout analog signals

11: Port0[3:2] are interconnected to UART_rx and UART_tx signals

Bit 5-4:

Sel_p054[1:0] Port0[5:4] I/O multiplexing scheme:

00: Port0[5:4] are interconnected to GPIO0[5:4] signals

01: Port0[5:4] are interconnected to DALI_rx and DALI_tx signals

10: Port0[5:4] are interconnected to I

C_scl and I

C_sda signals

11: Port0[5:4] are interconnected to UART_rx and UART_tx signals

Bit 7-6:

RFU reserved; in order to guarantee future compatibility, the bits are kept or set to 0

during register write operations

Offset: 0x2A

Default value: 0x00

6543

210

RFU

Sel_p054[1:0]

Sel_p032[1:0]

Sel_p010[1:0]

r/w

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