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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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MC705C9ACPE Datasheet(PDF) 56 Page - Freescale Semiconductor, Inc |
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MC705C9ACPE Datasheet(HTML) 56 Page - Freescale Semiconductor, Inc |
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56 / 118 page  Capture/Compare Timer MC68HC05C9A Advance Information Data Sheet, Rev. 4.1 56 Freescale Semiconductor 8.3.5 Input Capture Registers When a selected edge occurs on the TCAP pin, the current high and low bytes of the 16-bit counter are latched into the input capture registers (ICRH and ICRL). Reading ICRH before reading ICRL inhibits further capture until ICRL is read. Reading ICRL after reading the status register clears the input capture flag (ICF). Writing to the input capture registers has no effect. Figure 8-6. Input Capture Registers (ICRH and ICRL) NOTE To prevent interrupts from occurring between readings of ICRH and ICRL, set the interrupt flag in the condition code register before reading ICRH, and clear the flag after reading ICRL. 8.3.6 Output Compare Registers When the value of the 16-bit counter matches the value in the output compare registers (OCRH and OCRL), the planned TCMP pin action takes place. Writing to OCRH before writing to OCRL inhibits timer compares until OCRL is written. Reading or writing to OCRL after the timer status register clears the output compare flag (OCF). Figure 8-7. Output Compare Registers (OCRH and OCRL) ICRH $0014 Bit 7 654321 Bit 0 Read: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Write: Reset: Unaffected by reset ICRL $0015 Bit 7 654321 Bit 0 Read: Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0 Write: Reset: Unaffected by reset = Unimplemented OCRH $0016 Bit 7 654321 Bit 0 Write: Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Read: Reset: Unaffected by reset OCRL $0017 Bit 7 654321 Bit 0 Read: Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0 Write: Reset: Unaffected by reset |
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