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OMAP3530ECBB Datasheet(PDF) 39 Page - Texas Instruments

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No. de pieza OMAP3530ECBB
Descripción Electrónicos  OMAP3530/25 Applications Processor: OMAP 3 Architecture
PDF  264 Pages
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

OMAP3530ECBB Datasheet(HTML) 39 Page - Texas Instruments

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OMAP3530/25 Applications Processor
www.ti.com
SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009
Table 2-1. Ball Characteristics (CBB Pkg.) (continued)
BALL
BALL TOP
PIN NAME
MODE [4]
TYPE [5]
BALL
BALL
RESET REL. POWER [9]
HYS [10]
BUFFER
PULLUP
IO CELL [13]
BOTTOM [1] [2]
[3]
RESET
RESET REL. MODE [8]
STRENG TH /DOWN
STATE [6]
STATE [7]
(mA) [11]
TYPE [12]
T21
NA
mcbsp_clks
0
I
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
cam_ shutter 2
O
gpio_160
4
IO
uart1_cts
5
I
safe_mode
7
K26
NA
mcbsp1_fsx
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
mcspi4_cs0
1
IO
mcbsp3_fsx
2
IO
gpio_161
4
IO
safe_mode
7
W21
NA
mcbsp1_
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
clkx
mcbsp3_
2
IO
clkx
gpio_162
4
IO
safe_mode
7
H18
NA
uart3_cts_
0
IO
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
rctx
gpio_163
4
IO
safe_mode
7
H19
NA
uart3_rts_ sd 0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_164
4
IO
safe_mode
7
H20
NA
uart3_rx_ irrx 0
I
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_165
4
IO
safe_mode
7
H21
NA
uart3_tx_ irtx 0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_166
4
IO
safe_mode
7
T28
NA
hsusb0_clk
0
I
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_120
4
IO
safe_mode
7
T25
NA
hsusb0_stp
0
O
H
H
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_121
4
IO
safe_mode
7
R28
NA
hsusb0_dir
0
I
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_122
4
IO
safe_mode
7
T26
NA
hsusb0_nxt
0
I
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
gpio_124
4
IO
safe_mode
7
T27
NA
hsusb0_
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
data0
uart3_tx_ irtx 2
O
gpio_125
4
IO
safe_mode
7
U28
NA
hsusb0_
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
data1
uart3_rx_ irrx 2
I
gpio_130
4
IO
safe_mode
7
U27
NA
hsusb0_
0
IO
L
L
7
vdds
Yes
4
PU/ PD
LVCMOS
data2
uart3_rts_ sd 2
O
gpio_131
4
IO
safe_mode
7
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TERMINAL DESCRIPTION
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