93C76C datasheet(6/36 Pages) MICROCHIP

6 / 36 page

93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C

DS21796M-page 6

 2003-2012 Microchip Technology Inc.

2.4

Erase

The ERASE instruction forces all data bits of the

specified address to the logical ‘1’ state. The rising

edge of CLK before the last address bit initiates the

write cycle.

The DO pin indicates the Ready/Busy status of the

device if CS is brought high after a minimum of 250 ns

low (TCSL). DO at logical ‘0’ indicates that programming

is still in progress. DO at logical ‘1’ indicates that the

the device is ready for another instruction.

FIGURE 2-1:

ERASE TIMING

2.5

Erase All (ERAL)

The Erase All (ERAL) instruction will erase the entire

memory array to the logical ‘1’ state. The ERAL cycle

is identical to the erase cycle, except for the different

opcode. The ERAL cycle is completely self-timed. The

rising edge of CLK before the last data bit initiates the

write cycle. Clocking of the CLK pin is not necessary

after the device has entered the ERAL cycle.

The DO pin indicates the Ready/Busy status of the

device, if CS is brought high after a minimum of 250 ns

low (TCSL).

VCC must be

4.5V for proper operation of ERAL.

FIGURE 2-2:

ERAL TIMING

Note:

After the Erase cycle is complete, issuing

a Start bit and then taking CS low will clear

the Ready/Busy status from DO.

CLK

TCSL

Check Status

AN-1

AN-2

•••

TSV

TCZ

Busy

Ready

High-Z

TWC

High-Z

Note:

After the ERAL command is complete,

issuing a Start bit and then taking CS low

will clear the Ready/Busy status from DO.

CLK

TCSL

Check Status

•••

TSV

TCZ

Busy

Ready

High-Z

TEC

High-Z

93C76C Datasheet(PDF) 6 Page - Microchip Technology

93C76C Datasheet(HTML) 6 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Descarga

Enlace URL