MPC860DP datasheet(33/76 Pages) MOTOROLA

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MOTOROLA

MPC860 Family Hardware Speciﬁcations

Bus Signal Timing

Figure 9-21. Asynchronous External Master—Control Signals Negation Timing

Table 9-7 provides interrupt timing for the MPC860.

Figure 9-22 provides the interrupt detection timing for the external level-sensitive lines.

Figure 9-22. Interrupt Detection Timing for External Level Sensitive Lines

Figure 9-23 provides the interrupt detection timing for the external edge-sensitive lines.

Table 9-7. Interrupt Timing

Num

Characteristic 1

1 The timings I39 and I40 describe the testing conditions under which the IRQ lines are tested when being deﬁned as

level sensitive. The IRQ lines are synchronized internally and do not have to be asserted or negated with reference

to the CLKOUT.

The timings I41, I42, and I43 are speciﬁed to allow the correct function of the IRQ lines detection circuitry, and has

no direct relation with the total system interrupt latency that the MPC860 is able to support.

All Frequencies

Unit

Min

Max

I39

IRQx valid to CLKOUT rising edge (setup time)

6.00

—

I40

IRQx hold time after CLKOUT

2.00

—

I41

IRQx pulse width low

3.00

—

I42

IRQx pulse width high

3.00

—

I43

IRQx edge-to-edge time

× TCLOCKOUT

——

CSx, WE[0:3],

OE, GPLx,

BS[0:3]

B43

CLKOUT

IRQx

I39

I40

MPC860DP Datasheet(PDF) 33 Page - Motorola, Inc

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