AD9508

Data Sheet

Rev. A | Page 6 of 40

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

OUTPUT LOGIC SKEW1

CMOS load = 10 pF and LVDS load = 100 Ω

LVDS Output(s) and HSTL Output(s)

77

119

ps

Outputs on the same device; assumes

worst-case output combination

LVDS Output(s) and CMOS Output(s)

497

700

ps

Outputs on the same device; assumes

worst-case output combination

HSTL Output(s) and CMOS Output(s)

424

622

ps

Outputs on the same device; assumes

worst-case output combination

1

Output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.

LOGIC INPUTS

Table 4.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC INPUTS RESET, SYNC, IN_SEL

Input Voltage

High

1.7

V

2.5 V supply voltage operation

2.0

V

3.3 V supply voltage operation

Low

0.7

V

2.5 V supply voltage operation

0.8

V

3.3 V supply voltage operation

Input Current

−300

+100

µA

Input Capacitance

2

pF

SERIAL PORT SPECIFICATIONS—SPI MODE

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

CS

SCLK has a 200 kΩ internal pull-down resistor

Input Voltage

Logic 1

VDD − 0.4

V

Logic 0

0.4

V

Input Current

Logic 1

−4

µA

Logic 0

−85

µA

Input Capacitance

2

µA

SCLK

Input Voltage

Logic 1

VDD − 0.4

V

Logic 0

0.4

V

Input Current

Logic 1

70

µA

Logic 0

13

µA

Input Capacitance

2

pF

SDIO

As Input

Input Voltage

Logic 1

VDD − 0.4

V

Logic 0

0.4

V

Input Current

Logic 1

−1

µA

Logic 0

−1

µA

Input Capacitance

2

pF