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OR3LP26B Datasheet(PDF) 147 Page - Agere Systems |
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OR3LP26B Datasheet(HTML) 147 Page - Agere Systems |
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147 / 184 page  Lucent Technologies Inc. 147 Data Sheet ORCA OR3LP26B FPSC March 2000 Embedded Master/Target PCI Interface Lucent Technologies Inc. Timing Characteristics (continued) Table 65. OR3LP26B FPGA Side Interface Input Setup Delays, pciclk Synchronous Signals OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C. Note: The input setup parameters are measured from the pciclk clock output pin on the FPGA side, excluding the interbufs, which traverse the ASIC/FPGA boundary. The ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the clock and data paths. Table 66. OR3LP26B FPGA Side Interface Input Setup Delays, fclk Synchronous Signals OR3LP26B Commercial: VDD = 3.0 V to 3.6 V, 0 °C < TA < 70 °C; VDD2 = 2.38 V to 2.63 V, 0 °C < TA < 70 °C. Note: The input setup parameters are measured from the FCLK1 and FCLK2 clock input pins on the FPGA side, excluding the interbufs, which traverse the ASIC/FPGA boundary. The ORCA Foundry Static Analysis Tool, Trace, accounts for clock skew and interbuf delays on the clock and data paths. Description (TI = 85 °C, VDD = min, VDD2 = min) Min Max Unit fpga_mbusyn –0.514 — ns deltrn –1.486 — ns mwpcihold –1.190 — ns fpga_mstopburstn –1.208 — ns fpga_tabort 1.744 — ns fpga_tretryn 0.864 — ns twburstpendn –1.561 — ns trpcihold –1.542 — ns trburstpendn –1.557 — ns fpga_syserror –0.828 — ns Description (TI = 85 °C, VDD = min, VDD2 = min) Min Max Unit mcfgshiftenn 1.752 — ns maenn 4.777 — ns mfifoclrn 5.934 — ns mcmd[3:0] 5.251 — ns mwdataenn 4.806 — ns datafmfpga[63:0] (dual-port mode) 5.333 — ns datafmfpgax[7:0] (dual-port mode) 5.978 — ns mwdata[35:0] (quad-port mode) 5.978 — ns trdata[35:0] (quad-port mode) 5.226 — ns mwlastcycn 4.896 — ns mrdataenn 3.246 — ns tcfgshiftenn 1.209 — ns tfifoclrn 3.395 — ns taenn 3.893 — ns twdataenn 3.677 — ns trdataenn 3.773 — ns |
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