BUF04

REV. 0

–4–

WAFER TEST LIMITS

Parameter

Symbol

Conditions

Limit

Units

Offset Voltage

±15 V

1

mV max

±5 V

2

mV max

Input Bias Current

5

µA max

Power Supply Rejection Ratio

PSRR

V =

±4.5 V to ±18 V

76

dB

Output Voltage Range

Ω±10.5

V min

Supply Current

8.5

mA max

Gain

±10 V, R

Ω

1

± 0.005

V/V

NOTE

Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard

product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing.

ABSOLUTE MAXIMUM RATINGS

1

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±18 V

Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

±18 V

Maximum Power Dissipation . . . . . . . . . . . . . . . See Figure 16

Storage Temperature Range

Z Package . . . . . . . . . . . . . . . . . . . . . . . . . –65

°C to +175°C

P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65

°C to +150°C

Operating Temperature Range

BUF04Z . . . . . . . . . . . . . . . . . . . . . . . . . . –55

°C to +125°C

BUF04S, P . . . . . . . . . . . . . . . . . . . . . . . . . –40

°C to +85°C

Junction Temperature Range

Z Package . . . . . . . . . . . . . . . . . . . . . . . . . –65

°C to +150°C

P, S Package . . . . . . . . . . . . . . . . . . . . . . . –65

°C to +150°C

Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300

°C

Package Type

θ

JA

2

θ

JC

Units

8-Pin Cerdip (Z)

148

16

°C/W

8-Pin Plastic DIP (P)

103

43

°C/W

8-Pin SOIC (S)

158

43

°C/W

NOTES

otherwise noted.

2

θ

for cerdip, P-DIP, and LCC packages;

θ

board for SOIC package.

ORDERING GUIDE

Temperature

Package

Package

Model

Range

Description

Option

BUF04AZ/883

–55

°C to +125°C

Cerdip

Q-8

BUF04GP

–40

°C to +85°C

Plastic DIP

N-8

BUF04GS

–40

°C to +85°C

SO

SO-8

BUF04GBC

+25

°C

DICE

DICE

DICE CHARACTERISTICS

BUF04 Die Size 0.075 x 0.064 inch, 5,280 Sq. Mils

Substrate (Die Backside) Is Connected to V+

Transistor Count 45.