AD7945ARS-B datasheet(6/16 Pages) AD

6 / 16 page

AD7943/AD7945/AD7948

REV. B

–6–

AD7945 TIMING SPECIFICATIONS1 (T

A = TMIN to TMAX, unless otherwise noted)

Limit @

Parameter

VDD = +3 V to +3.6 V

VDD = +4.5 V to +5.5 V

Units

Description

tDS

ns min

Data Setup Time

tDH

ns min

Data Hold Time

tCS

ns min

Chip Select Setup Time

tCH

ns min

Chip Select Hold Time

tWR

ns min

Write Pulsewidth

NOTES

1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

Specifications subject to change without notice.

DATA VALID

tCH

tDS

tDH

DB11–DB0

tCS

tWR

Figure 3. AD7945 Timing Diagram

AD7948 TIMING SPECIFICATIONS1 (T

A = TMIN to TMAX, unless otherwise noted)

Limit @

Parameter

VDD = +3 V to +3.6 V

VDD = +4.5 V to +5.5 V

Units

Description

tDS

ns min

Data Setup Time

tDH

ns min

Data Hold Time

tCWS

ns min

CSMSB or CSLSB to WR Setup Time

tCWH

ns min

CSMSB or CSLSB to WR Hold Time

tLWS

ns min

LDAC to WR Setup Time

tLWH

ns min

LDAC to WR Hold Time

tWR

ns min

Write Pulsewidth

NOTES

1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

Specifications subject to change without notice.

DATA

VALID

DATA

VALID

tCWS

tCWH

tCWS

tCWH

tLWH

tLWS

tDH

tDS

tWR

tDH

tDS

CSMSB

CSLSB

LDAC

DB7–DB0

Figure 4. AD7948 Timing Diagram

AD7945ARS-B Datasheet(PDF) 6 Page - Analog Devices

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