AD53040

–6–

REV. B

1

9

2

10

3

11

4

12

5

13

6

14

7

15

8

1

JP3

–5.2V

C21

0.1 F

R4

50

R3

50

–2V

C14

0.1 F

R6

50

7

5

2

3

C12

0.01 F

50

J4

J3

U3

AD53040

THERM

C1

0.1 F

C2

0.1 F

50

–5.2V

C22

0.1 F

R1

50

R2

50

–2V

C15

0.1 F

R5

50

7

5

2

3

C13

0.01 F

50

J5

J6

50

50

50

C17

0.039 F

50

C16

0.039 F

TEST_LD

C18

5pF

C10

0.1 F

C9

0.1 F

C11

0.1 F

C19

0.1 F

R7

50

GND

1

JP1

GND

1

JP2

DATA

INH

J1

SMB

J2

SMB

U2

MC10EL16

U1

MC10EL16

P1

DB15

C4

1 F

C7

1 F

C6

1 F

C5

1 F

C8

0.1 F

–2V

THERM

–5.2V

–5.2V

DATA

NOTE:

1. 50

TERMINATION TO BE AS CLOSE TO RECEIVER

AS POSSIBLE. (END OF TRACE MARKED BY *). THROUGH

SMA CONNECTS BETWEEN MC10EL16 OUTPUTS AND DUT.

2. NO VIAS ALLOWED ON VOUT LINE.

IMPEDANCE MATCH.

4. ONE DIMENSION OF BOARD TO BE 4-1/2 INCHES.

5. DUT PACKAGE IS TO BE CENTERED ON BOARD.

6. ALL RESISTORS AND NONELECTROLYTIC CAPS ARE

0805-SIZE SURFACE MOUNT.

7. SEE DATA SHEET FOR HIDDEN POWER AND GROUND PINS

ON LOGIC GATES.

8. ALL 100nF BYPASS CAPACITORS TO BE LOCATED CLOSE

TO PACKAGE.

9. PCB IS TO BE 4-LAYER WITH POWER GND (

) AND –2V AS

INNER PLANES.

VL

VH

INH

C3

0.1 F

SMB

SMB

SMB

SMB

HQG1

G2H

IL+

G2L

IL–

PWR

GND

TH

J8

SIDESMB

J7

SIDESMB

+

TP

TP

TP

6

8

1

6

8

1

Figure 3. Evaluation Board Schematic