ACE5372

Low Power Real-Time Clock (RTC)

VER 1.3

15

Transmission System of Interface

Communication protocol determines: circuits in the equipment which sends data through SDA bus are

regarded as emitters, contrarily, circuits in the equipment which receives data through SDA bus are

regarded as receivers. Master equipment and master circuit control data transmission; Slave circuit is

controlled.

Typical System Bus Structure

Data Validity Protocol

Data transmission protocol determines: Transmit one bit data in every clock cycle. SDA must be kept at

a certain state while SCL is at the “H” state as shown below during data transmission.

Start and stop conditions

The SCL and SDA pins are at the “H” level when no data transmission is made. Changing the SDA from

“H” to “L” when the SCL and the SDA are “H” activates the start condition and access is started. Changing

the SDA from “L” to “H” when the SCL is “H” activates stop condition and accessing stopped.

Start and stop conditions