SC187 datasheet(13/17 Pages) SEMTECH

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SC187

Applications Information (continued)

OSTD

OUT

where V

OSTD is the pre-determined output voltage via the

CTL pins.

FF is needed to maintain good transient response perfor-

mance. The correct value of C

FF can be found using the

following equation.

)

(

]

[

]

[

OSTD

OUT

To simplify the design, it is recommended to program the

desired output voltage from a standard 1.0V as shown in

Figure 2 with a proper C

FF calculated from Equation 2. For

programming the output voltage from other standard

voltages, R

FB1, RFB2 and CFF need to be adjusted to conform

to the previous equations.

Shut Down

When all CTL pins are low, the device will run in shutdown

mode, drawing less than 1μA from the input power supply.

The internal switches and band-gap voltage will be imme-

diately turned off.

Thermal Shutdown

The device has a thermal shutdown feature to protect the

SC187 if the junction temperature exceeds 160°C. During

thermal shutdown, the on-chip power devices are dis-

abled, floating the LX output. When the temperature

drops by 10°C, it will initiate a soft start cycle to resume

normal operation.

Under-Voltage Lockout

Under-Voltage Lockout (UVLO) is enabled when the input

voltage drops below the UVLO threshold. This prevents

the device from entering an ambiguous state in which

regulation cannot be maintained. Hysteresis of approxi-

mately 300mV is included to prevent chattering near the

threshold. When the AVIN voltage rises back to the turn-

on threshold and CTL

X is high, the soft-start mode is

resumed.

Power Good

The power good (PGOOD) is an open-drain output. When

the output voltage drops below 10% of nominal voltage,

the PGOOD pin is pulled low after a 20μs delay. During

start-up, PGOOD will be asserted 2ms (typ.) after the

output voltage reaches 90% of the final regulation voltage.

The faults of over voltage, fold-back current limit mode

and thermal shutdown will force PGOOD low after a 20µs

delay. When recovering from a fault, PGOOD will be

asserted 1.8ms (typ.) after Vout reaches 90% of the final

regulation voltage.

Soft-Start

The soft-start mode is activated after AVIN reaches it’s

UVLO voltage threshold and CTL

X is set high to enable the

part. A thermal shutdown event will also activate the soft

start sequence. The soft-start mode controls the slew-rate

of the output voltage during start-up thus limiting in-rush

current on the input supply. During start-up, the reference

voltage for the error amplifier is clamped by the voltage

on the SS pin. The output voltage slew rate during soft-

start is determined by the value of the external capacitor

connected to the SS pin and the internal 5µA charging

current. The device requires a minimum soft-start time

from enable to final regulation in the order of 200µs,

including the 50µs enable delay. As a result the soft start

capacitor, Css, should be higher than 1.5nF.

100% Duty-Cycle Operation

SC187 is capable of operating at 100% duty-cycle. When

the difference between the input voltage and output

voltage is less than the minimum dropout voltage, the

PMOS switch is completely on, operating in 100% duty-

cycle. The minimum dropout voltage is the output current

multiplied by the on-resistance of the internal PMOS

switch and the DC-resistance of the inductor when PMOS

switch is on continuously.

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