WM8980CGEFLSLASHV datasheet(77/123 Pages) WOLFSON

77 / 123 page

Pre-Production

WM8980

PP, Rev 3.8, May 2012

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Audio

Interface

Control

MONO

Selects between stereo and mono

device operation:

0=Stereo device operation

1=Mono device operation. Data appears

in ‘left’ phase of LRC

ADCLRSWAP

Controls whether ADC data appears in

‘right’ or ‘left’ phases of LRC clock:

0=ADC data appear in ‘left’ phase of

LRC

1=ADC data appears in ‘right’ phase of

LRC

DACLRSWAP

Controls whether DAC data appears in

‘right’ or ‘left’ phases of LRC clock:

0=DAC data appear in ‘left’ phase of

LRC

1=DAC data appears in ‘right’ phase of

LRC

4:3

FMT

Audio interface Data Format Select:

00=Right Justified

01=Left Justified

10=I

2S format

11= DSP/PCM mode

6:5

Word length

00=16 bits

01=20 bits

10=24 bits

11=32 bits (see note)

LRP

right, left and i2s modes – LRCLK

polarity

1 = invert LRCLK polarity

0 = normal LRCLK polarity

DSP Mode – mode A/B select

1 = MSB is available o

n 1st BCLK rising

edge after LRC rising edge (mode B)

0 = MSB is available o

n 2nd BCLK rising

edge after LRC rising edge (mode A)

BCP

BCLK polarity

0=normal

1=inverted

Table 55 Audio Interface Control

ADCLRSWAP bit controls whether the ADC data appears in the right or left phase of the LRC clock

as defined for each audio format. Similarly, DACLRSWAP can be used to swap the left DAC data

from the left phase to the right phase of the LRC clock and the right DAC data from the right phase to

the left phase of the LRC clock.

Note: Right Justified Mode will only operate with a maximum of 24 bits. If 32-bit mode is selected, the

device will operate in 24-bit mode.

AUDIO INTERFACE CONTROL

The register bits controlling audio format, word length and master / slave mode are summarised

below. The audio interfaces can be controlled individually.

and LRC are outputs. The frequency of BCLK in master mode are controlled with BCLKDIV. These

are divided down versions of master clock. This may result in short BCLK pulses at the end of a LRC

if there is a non-integer ratio of BCLKs to LRC clocks.

WM8980CGEFL/V Datasheet(PDF) 77 Page - Wolfson Microelectronics plc

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